Laboratory 2 - Theory

Arithmetic instructions

ADD

Syntax:

add <regd>,<regs>; <regd> ← <regd> + <regs>
add <reg>,<mem>; <reg> ← <reg> + <mem>
add <mem>,<reg>; <mem> ← <mem> + <reg>
add <reg>,<con>; <reg> ← <reg> + <con>
add <mem>,<con>; <mem> ← <mem> + <con>

Semantics:

  • Both operands should have the same type: byte, word or doubleword.
  • While both operand can be registers, at most one operand can be a memory location.

Example:

add EDX,EBX; EDX ← EDX + EBX
add AX,[var]; AX ← AX + [var]
add [var],AX; [var] ← [var] + AX
add EAX,123456h; EAX ← EAX + 123456h
add BYTE [var],10; BYTE [var] ← BYTE [var] + 10

SUB

Syntax:

sub <regd>,<regs>; <regd> ← <regd> - <regs>
sub <reg>,<mem>; <reg> ← <reg> - <mem>
sub <mem>,<reg>; <mem> ← <mem> - <reg>
sub <reg>,<con>; <reg> ← <reg> - <con>
sub <mem>,<con>; <mem> ← <mem> - <con>

Semantics:

  • Both operands should have the same type: byte, word or doubleword.
  • While both operand can be registers, at most one operand can be a memory location.

Example:

sub EDX,EBX; EDX ← EDX - EBX
sub AX,[var]; AX ← AX - [var]
sub [var],AX; [var] ← [var] - AX
sub EAX,123456h; EAX ← EAX - 123456h
sub byte [var],10; BYTE [var] ← BYTE [var] - 10

MUL

Syntax:

mul <op8>; AX ← AL * <op8>
mul <op16>; DX:AX ← AX * <op16>
mul <op32>; EDX:EAX ← EAX * <op32>

Semantics:

  • The result of the multiplication operation is stored on double the size of the operands.
  • MUL instruction performs the multiplication operation for unsigned integers.
  • The first operand and the result are stored in registers.
  • Although the operation is binary, only one operand is specified, while the second operand and the location of the result are fixed.
  • The explicit operand can be a register or a variable, but it cannot be an immediate value (a constant).

Example:

mul DH; AX ← AL * DH
mul DX; DX:AX ← AX * DX
mul EBX; EDX:EAX ← EAX * EBX
mul BYTE [mem8]; AX ← AL * BYTE [mem8]
mul WORD [mem16]; DX:AX ← AX * WORD [mem8]

DIV

Syntax:

div <reg8>; AL ← AX / <reg8>, AH ← AX % <reg8>
div <reg16>; AX ← DX:AX / <reg16>, DX ← DX:AX % <reg16>
div <reg32>; EAX ← EDX:EAX / <reg32>, EDX ← EDX:EAX % <reg32>
div <mem8>; AL ← AX / <mem8>, AH ← AX % <mem8>
div <mem16>; AX ← DX:AX / <mem16>, DX ← DX:AX % <mem16>
div <mem32>; EAX ← EDX:EAX / <mem32>, EDX ← EDX:EAX % <mem32>

Semantics:

  • DIV instruction performs the division operation for unsigned integers.
  • The first operand and the result are stored in registers.
  • The first operand is not specified and is double the size of the second operand.
  • The explicit operand can be a register or a variable, but it cannot be an immediate value (a constant).
  • Dividing a large number by a small number, it is possible that the result exceeds the capacity of representation. In this case the same error is triggered as in the case of a division by 0.

Example:

div CL; AL ← AX / CL, AH ← AX % CL
div SI; AX ← DX:AX / SI, DX ← DX:AX % SI
div EBX; EAX ← EDX:EAX / EBX, EDX ← EDX:EAX % EBX

INC

Syntax:

inc <reg>; <reg> ← <reg> + 1
inc <mem>; <mem> ← <reg> + 1

Semantics:

  • Increments the value of the operand by 1.

Example:

inc DWORD [var]; DWORD [var] ← DWORD [var] + 1
inc EBX; EBX ← EBX + 1
inc DL; DL ← DL + 1

DEC

Syntax:

dec <reg>; <reg> ← <reg> - 1
dec <mem>; <mem> ← <reg> - 1

Semantics:

  • Decreases the value of the operand by 1.

Example:

dec EAX; EAX ← EAX - 1
dec BYTE [mem]; [value] ← [value] - 1

NEG

Syntax:

neg <reg>; <reg> ← 0 - <reg>
neg <mem>; <mem> ← 0 - <mem>

Semantics:

  • Arithmetic negation of the operand.

Example:

neg EAX; EAX ← 0 - EAX

Notations

<op8>    - operand on 8 bits
<op16>   - operand on 16 bits
<op32>   - operand on 32 bits

<reg8>   - register on 8 bits
<reg16>  - register on 16 bits
<reg32>  - register on 32 bits
<reg>    - register
<regd>   - destination register 
<regs>   - source register 

<mem8>   - memory variable on 8 bits
<mem16>  - memory variable on 16 bits
<mem32>  - memory variable on 32 bits
<mem>    - memory variable

<con8>   - constant (immediate value) on 8 bits
<con16>  - constant (immediate value) on 16 bits
<con32>  - constant (immediate value) on 32 bits
<con>    - constant (immediate value)